System in Package (SiP) integration is a major trend in the semiconductor packaging industry to reduce system form factor, costs and increase performance. Typical approaches are side by side (SbS) die arrangements, 3D die stacking (3D) and package on package (PoP) stacking.
Creating vertical interconnects for PoP and 3D is an expensive and space consuming factor. Due to needed production steps (e.g. etching, plating etc.), through silicon vias (TSVs) are very expensive, which makes an introduction for low cost packages critical. Through mold vias (TMVs) are typically realized either via embedded contact bars or laser drilling followed by a metal filling process. Both approaches require quite large design rules (DRs).